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[VHDL-FPGA-Verilog] SPIBusVerilog

Description: SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.
Platform: | Size: 398336 | Author: zhlm88 | Hits:

[Other Embeded program] Serial

Description: FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
Platform: | Size: 2048 | Author: feng | Hits:

[VHDL-FPGA-Verilog] uart_tran

Description: UART串口的传送verilog原程序，已经经过了编译仿真-Verilog UART serial transmission of the original procedure has been compiled after a simulation
Platform: | Size: 269312 | Author: 王迪 | Hits:

[Other] Verilog_PS2_RS232

Description: 实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上，并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。 -The realization of PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal and reception area in the data display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 1607680 | Author: chalin tong | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Platform: | Size: 56320 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] 16_FIR

Description: 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
Platform: | Size: 799744 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] SPI_verilog_vhdl

Description: SPI串口的内核实现（分别使用verilog和vhdl语言描述的）-The core of the realization of SPI serial port (using Verilog and VHDL language description of the)
Platform: | Size: 13312 | Author: 徐剑 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 8位双向移位寄存器: 实现串行数据与并行数据的转换,移位寄存数据功能的-8-bit bi-directional shift register: the realization of serial data and parallel data conversion, data storage function of displacement
Platform: | Size: 45056 | Author: 罗子 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232串口通信协议，verilog实现，通过FPGA完全调通。-RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
Platform: | Size: 3072 | Author: dingsheng | Hits:

[Other Embeded program] seqdet

Description: 对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
Platform: | Size: 18432 | Author: 刘建明 | Hits:

[VHDL-FPGA-Verilog] Verilogtextbook

Description: Verilog HDL的入门书籍，老外写的，语言简洁，是快速掌握Verilog编程的好教材，大家可以学习下-Verilog under the principle of serial communication, including receiving and sending the code. Through simulation, are a good example of Verilog study.
Platform: | Size: 5348352 | Author: clins | Hits:

[Embeded-SCM Develop] uart

Description: UART串口的verilog源代码，完全正确-UART serial Verilog source code, completely correct ...........
Platform: | Size: 33792 | Author: WangYong | Hits:

[Other Embeded program] UART

Description: 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5-The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
Platform: | Size: 285696 | Author: grqd | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_code

Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Platform: | Size: 1603584 | Author: shsh | Hits:

[Crack Hack] crc

Description: CRC校验码的实现，校验码6位，寄存器串行实现方式，经项目实际验证正确-CRC Check Code realization Check 6, register serial ways, the right to verify the actual project
Platform: | Size: 1024 | Author: fang | Hits:

[VHDL-FPGA-Verilog] A_bit_serial_data_transmitter

Description: 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify the correct behaviour of each component part by means of simulation. • To construct a top-level module corresponding to the Asynchronous Serial Data Transmitter, making use of the component parts developed above, and any additional behavioural elements which may be required. • To verify the correct operation of the top-level design by means of simulation using a Verilog-HDL test-fixture. • To automatically create a hierarchical logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
Platform: | Size: 2048 | Author: 吴德昊 | Hits:

[VHDL-FPGA-Verilog] TRL_Design_of_a_asynchronous_bit_serial_data_trans

Description: RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据，执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behaviour of the transmitter by means of simulation using a Verilog test-module. • To automatically create a logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
Platform: | Size: 2048 | Author: 吴德昊 | Hits:

[VHDL-FPGA-Verilog] tlc5615

Description: TLC5615串行DA的驱动接口,采用verilog编程-TLC5615 driver DA serial interface using verilog programming
Platform: | Size: 317440 | Author: 田文军 | Hits:

[Com Port] RS232

Description: 很好用的串口通讯程序，已经通过验证，用Verilog语言编写的放心使用了！-Good use of serial communication program has been validated using Verilog language used in the rest assured!
Platform: | Size: 54272 | Author: 宋振丰 | Hits:

[VHDL-FPGA-Verilog] uart_my

Description: 自己设计的串口verilog代码，已在fpga上跑过，问题无误。-Serial verilog design code, ran in the fpga, correct the problem.
Platform: | Size: 2048 | Author: 巴音 | Hits:
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